S3C6410-uboot详细解读之smdk6410.h

/*

* (C) Copyright 2002

* Sysgo Real-Time Solutions, GmbH

* Marius Groeger

* Gary Jennejohn

* David Mueller

*

* Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.

*

* See file CREDITS for list of people who contributed to this

* project.

*

* This program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of

* the License, or (at your option) any later version.

*

* This program is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

* GNU General Public License for more details.

*

* You should have received a copy of the GNU General Public License

* along with this program; if not, write to the Free Software

* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

* MA 02111-1307 USA

*/

/*

这里粗粗解释了配置文件，可能有很多错，还望各位前辈指出。

*/

#ifndef __CONFIG_H//config.h中定义了forlinx_boot_nand和forlinx_boot_ram256

#define __CONFIG_H

/*

* High Level Configuration Options

* (easy to change)

*/

#define CONFIG_S3C6410 1 /* in a SAMSUNG S3C6410 SoC */

#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */

#define CONFIG_SMDK6410 1 /* on a SAMSUNG SMDK6410 Board */

//#define CONFIG_SMDK6410_X** 1 /* on a SAMSUNG SMDK6410 OneNAND POP Board 不使用onenand*/

#define MEMORY_BASE_ADDRESS 0x50000000

/* input clock of PLL */

#define CONFIG_SYS_CLK_FREQ 12000000 /* the SMDK6400 has 12MHz input clock */

#ifdef FORLINX_BOOT_NAND

#define CONFIG_ENABLE_MMU

#endif

#ifdef CONFIG_ENABLE_MMU

#define virt_to_phys(x) virt_to_phy_smdk6410(x)

#else

#define virt_to_phys(x) (x)

#endif

#define CONFIG_MEMORY_UPPER_CODE//堆栈初始化代码

#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff不使用中断和快速中断 */

#define CONFIG_INCLUDE_TEST

#define CONFIG_ZIMAGE_BOOT?/引导内核命令

#define CONFIG_IMAGE_BOOT?/同上

#define BOARD_LATE_INIT?/延时操作

#define CONFIG_SETUP_MEMORY_TAGS?/ram信息标签，用于向内核传递uboot参数

#define CONFIG_CMDLINE_TAG?/同上 命令行标签

#define CONFIG_INITRD_TAG//同上 初始ram磁盘标签

/*

* Architecture magic and machine type

*/

#define MACH_TYPE 1626

#define UBOOT_MAGIC (0x43090000 | MACH_TYPE)

/* Power Management is enabled 电源管理*/

#define CONFIG_PM

#define CONFIG_DISPLAY_CPUINFO?/显示cpu型号

#define CONFIG_DISPLAY_BOARDINFO//显示板号

#undef CONFIG_SKIP_RELOCATE_UBOOT//不实用重定位

#undef CONFIG_USE_NOR_BOOT//不实用onenand

/*

* Size of malloc() pool申请的内存大小

*/

//#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 1024*1024)

#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data 初始数据大小*/

#define CFG_STACK_SIZE 512*1024?/堆栈大小

/*

* Hardware drivers无此外设

*/

//#define CONFIG_DRIVER_SMC911X 1 /* we have a SMC9115 on-board */

#ifdef CONFIG_DRIVER_SMC911X

#undef CONFIG_DRIVER_CS8900

#define CONFIG_DRIVER_SMC911X_BASE 0x18800300

#else

#define CONFIG_DRIVER_CS8900 0 /* we have a CS8900 on-board */

#define CS8900_BASE 0x18800300

#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */

#endif

/*

* select serial console configuration

*/

#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */

#define CFG_HUSH_PARSER /* use "hush" command parser */

#ifdef CFG_HUSH_PARSER

#define CFG_PROMPT_HUSH_PS2 "> "

#endif

#define CONFIG_CMDLINE_EDITING

//#undef CONFIG_S3C64XX_I2C /* this board has H/W I2C */

#define CONFIG_S3C64XX_I2C /*add by phantom*/

#ifdef CONFIG_S3C64XX_I2C

#define CONFIG_HARD_I2C 1

#define CFG_I2C_SPEED 10000?/I2C时钟SCL

#define CFG_I2C_SLAVE 0xFE?/I2C从属设备号

#endif

#define CONFIG_DOS_PARTITION//关于分区

#define CONFIG_SUPPORT_VFAT?

#define CONFIG_USB_OHCI

#undef CONFIG_USB_STORAGE

#define CONFIG_S3C_USBD

#define USBD_DOWN_ADDR 0xc0000000//usb下载地址dnw

/************************************************************

* RTC实时时钟

************************************************************/

#define CONFIG_RTC_S3C64XX 1

/* allow to overwrite serial and ethaddr */

#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE 115200

/***********************************************************

* Command definition

***********************************************************/

#define CONFIG_COMMANDS

(CONFIG_CMD_DFL |

CFG_CMD_CACHE |

CFG_CMD_USB |

CFG_CMD_REGINFO |

CFG_CMD_LOADS |

CFG_CMD_LOADB |

CFG_CMD_ENV |

CFG_CMD_NAND |

CFG_CMD_MOVINAND|

CFG_CMD_ONENAND |

CFG_CMD_DATE |

CFG_CMD_PING |

CFG_CMD_FAT |

CFG_CMD_ELF)

& ~(CFG_CMD_AUTOSCRIPT |

CFG_CMD_BOOTD |

CFG_CMD_IMI |

CFG_CMD_RUN |

CFG_CMD_CONSOLE |

CFG_CMD_DOCG3P3 |

CFG_CMD_EEPROM |

CFG_CMD_I2C |

0)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */

#include

#define CONFIG_BOOTDELAY 1

#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=yaffs2 console=ttySAC0,115200"

#define CONFIG_ETHADDR 00:40:5c:26:0a:5b

#define CONFIG_NETMASK 255.255.255.0

#define CONFIG_IPADDR 192.168.1.20

#define CONFIG_SERVERIP 192.168.1.10

#define CONFIG_GATEWAYIP 192.168.1.1

#define CONFIG_ZERO_BOOTDELAY_CHECK

/*#define CONFIG_NET_MULTI 1 */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)

#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */

/* what's this ? it's not used anywhere */

#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */

#endif

/*

* Miscellaneous configurable options

*/

#define CFG_LONGHELP /* undef to save memory */

#define CFG_PROMPT "SMDK6410 # " /* Monitor Command Prompt 命令提示符*/

#define CFG_CBSIZE 256 /* Console I/O Buffer Size控制台IO缓冲区大小 */

#define CFG_PBSIZE 384 /* Print Buffer Size打印缓冲大小 */

#define CFG_MAXARGS 16 /* max number of command args *大命令变量数16条*/

#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size 板子参数大小*/

#define CFG_MEMTEST_START MEMORY_BASE_ADDRESS /* memtest works on内存检测开始地址 */

#define CFG_MEMTEST_END MEMORY_BASE_ADDRESS + 0x7e00000 /* 128 MB in DRAM 结束地址*/

#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR MEMORY_BASE_ADDRESS /* default load address */

/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */

/* it to wrap 100 times (total 1562500) to get 1 sec. */

#define CFG_HZ 1562500 // at PCLK 50MHz像素始时钟

/* valid baudrates */

#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------

* Stack sizes

*

* The stack sizes are set up in start.S using the settings below

*/

#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */

#ifdef CONFIG_USE_IRQ

#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack 中断*/

#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack 异常中断*/

#endif

//#define CONFIG_CLK_800_133_66

//#define CONFIG_CLK_666_133_66

#define CONFIG_CLK_532_133_66

//#define CONFIG_CLK_400_133_66

//#define CONFIG_CLK_400_100_50

//#define CONFIG_CLK_OTHERS

#define CONFIG_CLKSRC_CLKUART

#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)

#if defined(CONFIG_CLK_666_133_66) /* FIN 12MHz, Fout 666MHz */

#define APLL_MDIV 333

#define APLL_PDIV 3

#define APLL_SDIV 1

#undef CONFIG_SYNC_MODE /* ASYNC MODE */

#elif defined(CONFIG_CLK_532_133_66) /* FIN 12MHz, Fout 532MHz */

#define APLL_MDIV 266

#define APLL_PDIV 3

#define APLL_SDIV 1

#define CONFIG_SYNC_MODE

#elif defined(CONFIG_CLK_400_133_66) || defined(CONFIG_CLK_800_133_66) /* FIN 12MHz, Fout 800MHz */

#define APLL_MDIV 400

#define APLL_PDIV 3

#define APLL_SDIV 1

#define CONFIG_SYNC_MODE

#elif defined(CONFIG_CLK_400_100_50) /* FIN 12MHz, Fout 400MHz */

#define APLL_MDIV 400

#define APLL_PDIV 3

#define APLL_SDIV 2

#define CONFIG_SYNC_MODE

#elif defined(CONFIG_CLK_OTHERS)

/*If you have to use another value, please define pll value here*/

/* FIN 12MHz, Fout 532MHz */

#define APLL_MDIV 266

#define APLL_PDIV 3

#define APLL_SDIV 1

#define CONFIG_SYNC_MODE

#else

#error "Not Support Fequency or Mode!! you have to setup right configuration."

#endif

#define CONFIG_UART_66 /* default clock value of CLK_UART */

#define APLL_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)

/* prevent overflow */

#define Startup_APLL (CONFIG_SYS_CLK_FREQ/(APLL_PDIV<

/* fixed MPLL 533MHz */

#define MPLL_MDIV 266

#define MPLL_PDIV 3

#define MPLL_SDIV 1

#define MPLL_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)

/* prevent overflow */

#define Startup_MPLL ((CONFIG_SYS_CLK_FREQ)/(MPLL_PDIV<

#if defined(CONFIG_CLK_800_133_66)

#define Startup_APLLdiv 0

#define Startup_HCLKx2div 2

#elif defined(CONFIG_CLK_400_133_66)

#define Startup_APLLdiv 1

#define Startup_HCLKx2div 2

#else

#define Startup_APLLdiv 0

#define Startup_HCLKx2div 1

#endif

#define Startup_PCLKdiv 3

#define Startup_HCLKdiv 1

#define Startup_MPLLdiv 1

#define CLK_DIV_VAL ((Startup_PCLKdiv<<12)|(Startup_HCLKx2div<<9)|(Startup_HCLKdiv<<8)|(Startup_MPLLdiv<<4)|Startup_APLLdiv)

#if defined(CONFIG_SYNC_MODE)

#define Startup_HCLK (Startup_APLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))

#else

#define Startup_HCLK (Startup_MPLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))

#endif

/*-----------------------------------------------------------------------

* Physical Memory Map物理内存映射

*/

#ifndef CONFIG_SMDK6410_X**

// 128 MB SDRAM

#if defined(FORLINX_BOOT_RAM128)

#define DMC1_MEM_CFG 0x00010012 /* Supports one CKE control, Chip1, Burst4, Row/Column bit */

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